During the high-speed transmission of digital data through a computer system such as a data storage device or communication system, it is extremely important to monitor the digital data for errors and to be able to correct any errors that may occur. Typical schemes for checking for errors and, in some cases, correcting errors, include the use of parity bits and error correction codes (ECC). Several methods incorporate both schemes in order to provide redundant error checking in the data transmission system.
One example of such a system is shown at 10 in FIG. 1. In system 10, the data is transmitted from upstream logic 12 to downstream logic 20. The data, along with the associated parity bits, are transmitted to a parity checker 14 which compares the parity of the transmitted data word with the parity bits to determine whether an error has occurred in either the data or the parity bits. The data, without the parity bits, is also transmitted to ECC generator 16, which generates an error correction code in accordance with known algorithms. The data with ECC is then transmitted to downstream logic 20. While this system incorporates both parity and ECC error detection schemes, it is still vulnerable to undetected errors because the data travels in separate paths to the parity checker 14 and the ECC generator 16. For example, if an error in the data were to occur at point 18, the parity checker 14 would indicate correct parity, but the ECC generated by the ECC generator 16 would be based on faulty data and would thus be incorrect. A similar error could occur if the data was corrupted in the path to the parity checker 14, if the corruption resulted in incorrect parity.
Another example of a system incorporating parity and ECC error checking schemes is shown at 30 in FIG. 2. Similar to system 10 of FIG. 1, system 30 transmits data from upstream logic 32 to downstream logic 42 and the parity of the data is checked in parity checker 34. However, in this system, the data is passed through two separate ECC generators 36, 38 and the resulting ECCs are compared to each other in comparator 40 before being passed to the downstream logic 40. This system 30 would be likely to detect any errors that occurred in the data downstream of intersection 44, since, if the data is corrupted in either of branches 46 and 48, the resulting ECC codes from ECC generators 36, 38 would be different and if the data is corrupted in branch 50, the parity checker 34 will detect a change in parity of the data. However, if the data is corrupted at point 52, both ECC generators will generate the same, incorrect ECC and, depending on the parity of the incorrect data, the parity checker 34 might not detect the error.